The implementation of arithmetic circuits is very important in digital signal processing and communications applications. Moreover, as circuit complexity continues to increase, power requirements of the equipment becomes more and more important, particularly in equipment developed for portable operation (and thus battery powered).
As is well-known, a summing of a vector of numbers is a common requirement in DSP systems—e.g., digital filters. In such DSP systems, an accumulation path with a long word-length is needed to prevent overflow. However, in many cases, when inputs to the accumulation path are of a small magnitude, only a short word length is needed to represent the magnitude of the input value.
Numerous design techniques are known for simplifying the complexity of arithmetic operations, and for otherwise reducing the power dissipation in digital arithmetic circuits. In particular, the 2's complement number signal representation has been widely used in arithmetic circuit design due to the ease of implementation of arithmetic functions. However, it is also well known that when a 2's complement number switches between a positive and negative value, large signal transmission activity occurs in the most-significant-bits (MSBs) of the data path. As will be apparent, such a high level of switching activity runs counter to an objective for low power operation. As is also well known, for small-valued input signals, a number of the MSBs in a 2's complement representation do not provide useful information.
While low power techniques that exploit the use of other types of signal representation are known in the art—e.g., sign-magnitude and signed-digit, the easy to implement properties of 2's complement arithmetic circuits are lost in those techniques.